1. Field of the Invention
The invention relates to asynchronous first in first out (FIFO) interface, and in particular relates to asynchronous FIFO interface in radio frequency (RF) apparatus.
2. Description of the Related Art
The popularity and requirement of wireless communication (e.g. cellular phones, wireless network) has led to market demand for communication systems with low cost, low power and small form-factor radio-frequency (RF) transceivers. Recently, analog transceivers, digital processors and clock generators have integrated on a single chip for satisfying the requirement of low cost, low power, and small form-factor RF transceivers. In the RF transceiver, the clock requirements of analog circuits and digital circuits are different. For example, the analog-to-digital converter (ADC) and digital-to-analog converter (DAC) in the analog circuits require low jitter clocks to increase the signal to noise ratio (SNR) while converting. The digital filters in the digital circuit require fixed frequency clock to prevent the filter shaping from being worse while the digital filter can tolerate high jitter clocks.
FIG. 1 is a block diagram of conventional RF transceiver 100 on a single chip. A RF front-end receiver 110 receives a first RF signal and down-converts the first RF signal to at least one first intermediate frequency (IF) signal according to at least one local signal generated by a local source 120. A RF front-end transmitter 112 transmits a second RF signal and up-converts at least one second IF signal to the second RF signal according to the at least one local signal. A clock source 150 generates a digital clock to a base-band processor 160, an ADC 130 and a DAC 132 for processing digital signals synchronously, However, the clock phases of each circuit, for example the ADC 130, the DAC 132 and the base-band processor 160, will be different due to practical circuit layout. That will lead to the digital signals transmission error. To prevent that problem, an interface, first in first out (FIFO) buffers, is added between the ADC 130, the DAC 132 and the base-band processor 160. FIG. 2 is a block diagram of conventional RF transceiver 200 with FIFO buffers on a single chip. Similarly, a RF front-end receiver 210 receives a first RF signal and down-converts the first RF signal to at least one first IF signal according to at least one local signal generated by a local source 220. A RF front-end transmitter 212 transmits a second RF signal and up-converts at least one second IF signal to the second RF signal according to the at least one local signal. A clock source 250 generates a digital clock to a base-band processor 260, an ADC 230, a DAC 232 and FIFO buffers 270 and 272. The clock source 250 provides synchronous digital clock to the base-band processor 260, the ADC 230, the DAC 232 and the FIFO buffers 270 and 272. Although the clock phases of each circuit may still be different, the blocks 270 and 272 can be buffers between the analog circuit and the digital circuit to prevent transmission from error.
However, the ADC 230, the DAC 232, the base-band processor 260 and the FIFO buffers 270 and 272 still operate synchronously. For synchronization, the ADC 230, the DAC 232 and the base-band processor 260 have to receive synchronous clock generated from the same clock source 250. Therefore, for satisfying the low jitter clock requirement of the ADC 230 and the DAC 232, the clock source 250 which also provides the digital clock to the digital circuits must be low jitter although the digital circuits do not require low jitter clock. The low jitter clock source, the clock source 250, will increase chip cost. However, a low jitter source, the local source 220 is existed in the conventional RF transceiver 200 for increasing SNR and reducing adjacent channel blocking effect while down-converting. If the clock of the ADC 230 and DAC 232 can be provided by the local source 220, the clock source 250 can be a high jitter source to reduce hardware cost, otherwise it can be a fixed frequency source. In this way, the RF transceiver may give rise to another problem. The clock of the ADC 230 and DAC 232 provided by the local source 220 may asynchronous to the clock of the base-band processor 260 provided by the clock source 250. The interface coupled between the ADC 230, DAC 232 and the base-band processor 260 should operate under asynchronous data communication.
Asynchronous FIFO interfaces and operation method thereof are thus desired.